(1) Field of the Invention
The invention relates to video signal processing, and more particularly, to a phase recovery method and circuit to generate an optimum phase shifted sampling clock for sampling a synchronized video signal having a synchronization signal pulse.
(2) Description of the Prior Art
Cathode ray tube, or CRT, monitors have traditionally dominated the field of desktop computers. However, with the advent of portable computers and handheld, smart devices, the use of flat panel and LCD displays has crown. Recently, flat panel displays have even taken market share in the desktop PC arena. The flat panel features of reduced weight and size offer significant advantages to designers and users.
CRT displays are typically driven using a VGA method wherein the display area is divided into an array of pixels having a number of horizontal and vertical lines. For example, a display area might be divided into 480 horizontal lines with each line having 640 segments or pixels. To display an image, the imaging beam begins at a top corner of the screen and then scans a single horizontal line. When this horizontal line is completed, the beam indexes vertically to the next horizontal line. The scanning continues until the entire screen has been updated with the current image. This process is repeated many times each second to insure good image quality and timely response.
Since the VGA method is very established in the art, it is desirable to make the digital, flat panel display technology compatible with this technique. To facilitate the use of digital displays with VGA drivers and video cards, a basic problem must be overcome. The video signals For the red, green, and blue (RGB) elements of each pixel are analog. However, these video signals must be converted to digital signals to drive the digital pixels of the flat panel display. Therefore, analog-to-digital video signal processing must be performed.
Referring now to FIG. 1, a prior art video processing block 10 or circuit is shown. In this circuit 10, a sample and hold is performed on the analog video input A(t). For example, A(t) might be one of the color signals from a VGA driver card of a PC. Alternatively, A(t) might be a television video signal. The purpose of the sample and hold circuit 10 is to sample the analog video signal A(t) at a fixed time interval governed by the sampling clock clk_s. The sampled value of A(t) is denoted Si where Si is the value at the clk_s cycle . After the sampled value Si is generated, this value may then be converted to a digital value in an analog-to-digital converter (ADC).
Referring now to FIG. 2, two timing diagrams are shown to illustrate a potential problem in the sampling process. In the timing diagrams, the analog video signal A(t) and the sampling clock clk_s are shown. The A(t) signal 11 has two states: the pixel value state 18 and the transition state 22. Each pixel value state 18 corresponds to a single location on the display. A(t) changes from pixel state 18 to pixel state 18 such that an entire image line is transmitted serially. The transition times 22 represent a time when the video signal A(t) 11 is in an invalid data state.
As discussed above, the video signal A(t) 11 is sampled at time points governed by the sampling clock clk_s 12 and 13. In this example, the sample points are the rising edges 14 of clk_s. In the first pair of signals A(t) 11 and clk_s 12, the rising edges of the sample clock clk_s are aligned with the transition phase of the video signal A(t). Therefore, the sampled data S1 will be severely distorted. The sampling clock clk_s is said to be in the wrong phase with respect to the video data.
In the second pair of signals A(t) 11 and clk_s 13, the sampling clock phase is moved to a correct relationship. The rising edges of clk_s occur during the valid pixel data phase of the video signal A(t). Therefore, the sampled video signal Si should be valid. It can be clearly seen that the phase arrangement of the sampling clock clk_s with respect to the video signal A(t) is a critical element in achieving an accurate sample data stream S1 and, ultimately, accurate image reproduction on the digital display. This phase alignment is commonly called phase recovery.
Referring now to FIG. 3, a prior art method for phase recovery is shown. This prior art method is called an energy accumulation phase recovery method. This method monitors the accumulated energy of the video samples Si at a series of different clock phase arrangements. The phase with the greatest accumulated sample energy is determined to be the correct sample phase.
Referring now to FIG. 4, timing diagrams depicting the energy accumulation method are shown. Note first the synchronization signal SYNC.50. SYNC 50 is a standard signal from the VGA drive circuitry. The SYNC pulse occurs between each horizontal line of image data sent on the video signal A(t) 52. The SYNC pulse is used to synchronize or label the next line of data. More specifically, the trailing edge 60 of the SYNC pulse indicates that the pixel stream for the next horizontal line of data is about to be transmitted on A(t) after a specified wait time. In this case, the wait time between the trailing edge 60 of the SYNC pulse 50 and the first pixel transition of A(t) is a period commonly called the BACKPORCH. The BACKPORCH time determines how long the sampling circuit must wait until valid samples of the video signal A(t) can begin. Unfortunately, it is not possible for the video processing circuit to know with certainty the exact BACKPORCH time from the VGA driver.
Several sampling clocks, clk_s054, clk_s156, and clk_sk 58, are shown. Each sample clock represents a different sample clock phase that could be used for sampling the video signal A(t) 52. Referring again to FIG. 3, in the energy accumulation method, the phase is initialized to zero, which represents clk_s0, in step 30. Next, this zero phase is used to sample the video signal. Referring again to FIG. 4, A(t) 52 is sampled by clk_s0 at the rising edges 64. Referring again to FIG. 3, the energy of the sample stream Si, which is proportional to (Si)2, is stored and summed in step 34 from the first sample to sample m where the VGA system is set for a display width of m pixels. Next, the phase of the sample clock is shifted in step 38. If the last phase shift, k, has not been complete in step 42, then the process is repeated. After the energy of all of the phases has been accumulated, the maximum phase shift is selected in step 46.
There are several significant problems with the conventional energy accumulation method of FIGS. 3 and 4. First, in cases where a large display matrix is used, the SYNC period (the time between SYNC pulses) can be very large. In this case, a complex accumulation circuit must be used to accumulate the energy of a large number of samples S1. Second, if there is little or no variation in the voltage level of the video signal A(t), then this method does not work. For example, in the case of an all blue image, or blue screen, the video signal is nearly a constant DC level without transitions. In this case, the method cannot distinguish the maximum energy level and will fail. Third, if significant ground noise is present in the system, then this noise will be accumulated with the sample stream Si. This noise can easily cause a wrong phase to be selected.
Several prior art inventions describe video signal processing methods and circuits. U.S. Pat. No. 6,108,043 to White describes a circuit for processing SYNC signals having different duration. U.S. Pat. No. 6,144,413 to Zatsman discloses a method and an apparatus for sampling a video signal. The method detects differences between samples of a filtered SYNC signal to determine the best sampling phase. U.S. Pat. No 6,233,020 to Wilber teaches a phase lock loop circuit for use in video processing.